C8051F93X Datasheet, PDF (131/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 11.1. SFR Page: SFR Page
Bit
7
6
5
4
3
2
1
0
Name
SFRPAGE[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xA7
Bit
Name
Function
7:0 SFRPAGE[7:0] SFR Page.
Specifies the SFR Page used when reading, writing, or modifying special function
registers.
Table 11.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
ACC
0xE0
All Accumulator
ADC0AC
0xBA
0x0 ADC0 Accumulator Configuration
ADC0CF
0xBC
0x0 ADC0 Configuration
ADC0CN
0xE8
0x0 ADC0 Control
ADC0GTH
0xC4
0x0 ADC0 Greater-Than Compare High
ADC0GTL
0xC3
0x0 ADC0 Greater-Than Compare Low
ADC0H
0xBE
0x0 ADC0 High
ADC0L
0xBD
0x0 ADC0 Low
ADC0LTH
0xC6
0x0 ADC0 Less-Than Compare Word High
ADC0LTL
0xC5
0x0 ADC0 Less-Than Compare Word Low
ADC0MX
0xBB
0x0 AMUX0 Channel Select
ADC0PWR
0xBA
0xF ADC0 Burst Mode Power-Up Time
ADC0TK
0xBD
0xF ADC0 Tracking Control
B
0xF0
All B Register
CKCON
0x8E
0x0 Clock Control
CLKSEL
0xA9
All Clock Select
CPT0CN
0x9B
0x0 Comparator0 Control
CPT0MD
0x9D
0x0 Comparator0 Mode Selection
CPT0MX
0x9F
0x0 Comparator0 Mux Selection
CPT1CN
0x9A
0x0 Comparator1 Control
Page
110
77
76
75
81
81
80
80
82
82
85
78
79
110
284
197
97
97
101
98
Rev. 1.3
131