C8051F93X Datasheet, PDF (187/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Important Notes:
• The Power-on Reset (POR) delay is not incurred after a VDD/DC+ supply monitor reset. See Section
“4. Electrical Characteristics” on page 45 for complete electrical characteristics of the VDD/DC+ moni-
tor.
• Software should take care not to inadvertently disable the V_DD Monitor as a reset source when writing
to RSTSRC to enable other reset sources or to trigger a software reset. All writes to RSTSRC should
explicitly set PORSF to '1' to keep the V_DD Monitor enabled as a reset source.
• The VDD/DC+ supply monitor must be enabled before selecting it as a reset source. Selecting the
VDD/DC+ supply monitor as a reset source before it has stabilized may generate a system reset. In
systems where this reset would be undesirable, a delay should be introduced between enabling the
VDD/DC+ supply monitor and selecting it as a reset source. See Section “4. Electrical Characteristics”
on page 45 for minimum VDD/DC+ Supply Monitor turn-on time. No delay should be introduced in
systems where software contains routines that erase or write Flash memory. The procedure for
enabling the VDD/DC+ supply monitor and selecting it as a reset source is shown below:
1. Enable the VDD/DC+ Supply Monitor (VDMEN bit in VDM0CN = 1).
2. Wait for the VDD/DC+ Supply Monitor to stabilize (optional).
3. Select the VDD/DC+ Supply Monitor as a reset source (PORSF bit in RSTSRC = 1).
SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control
Bit
7
6
5
4
3
2
1
0
Name VDMEN VDDSTAT VDDOK Reserved Reserved Reserved
Type
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Reset
1
Varies
Varies
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xFF
Bit
Name
Function
7
VDMEN VDD/DC+ Supply Monitor Enable.
This bit turns the VDD/DC+ supply monitor circuit on/off. The VDD/DC+ Supply
Monitor cannot generate system resets until it is also selected as a reset source in
register RSTSRC (SFR Definition 18.2).
0: VDD/DC+ Supply Monitor Disabled.
1: VDD/DC+ Supply Monitor Enabled.
6 VDDSTAT VDD/DC+ Supply Status.
This bit indicates the current power supply status.
0: VDD/DC+ is at or below the V_RST threshold.
1: VDD/DC+ is above the V_RST threshold.
5
VDDOK VDD/DC+ Supply Status (Early Warning).
This bit indicates the current power supply status.
0: VDD/DC+ is at or below the V_WARN threshold.
1: VDD/DC+ is above the V_WARN monitor threshold.
4:2 Reserved Reserved.
Read = 000b. Must Write 000b.
1:0 Unused Unused.
Read = 00b. Write = Don’t Care.
Rev. 1.3
187