C8051F93X Datasheet, PDF (281/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
NSS
T_SE
SCK*
T
CKH
T_CKL
T
SIS
T
SIH
MOSI
MISO
T
SEZ
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
Figure 24.10. SPI Slave Timing (CKPHA = 0)
T_SD
T
SDZ
NSS
T_SE
T_CKL
T_SD
SCK*
T
CKH
T
SIS
T
SIH
MOSI
T_SEZ
MISO
T
SOH
* SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1.
T
SLH
T
SDZ
Figure 24.11. SPI Slave Timing (CKPHA = 1)
Rev. 1.3
281