C8051F93X Datasheet, PDF (59/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 4.4. Reset Electrical Characteristics
V_DD = 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
Conditions
I_OL = 1.4 mA,
V_DD = 2.0 to 3.6 V
V_DD = 0.9 to 2.0 V
V_DD = 2.0 to 3.6 V
V_DD = 0.9 to 2.0 V
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
Min Typ Max Units
—
—
0.6
V
V_DD – 0.6 —
—
V
0.7 x V_DD —
—
V
—
—
0.6
V
—
— 0.3 x V_DD V
—
—
4
20
—
30
µA
VDD/DC+ Monitor Thresh- ^{Early Warning}
old (V_RST)
Reset Trigger
(all power modes except Sleep)
1.8 1.85 1.9
V
1.7 1.75 1.8
VBAT Ramp Time for
Power On
One-cell Mode: VBAT Ramp 0–0.9 V
Two-cell Mode: VBAT Ramp 0–1.8 V
—
—
3
ms
Initial Power-On (VBAT Rising)
—
0.75
—
VBAT Monitor Threshold
(V_POR)
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
0.7
—
0.8
0.95
0.9
—
V
Missing Clock Detector
Timeout
Time from last system clock rising edge
to reset initiation
100
650 1000
µs
Minimum System Clock w/ _{System clock frequency which triggers}
Missing Clock Detector
a missing clock detector timeout
—
7
10
kHz
Enabled
Reset Time Delay
Delay between release of any reset
source and code 
execution at location 0x0000
Minimum RST Low Time to
Generate a System Reset
—
10
—
µs
15
—
—
µs
V_DD Monitor Turn-on Time
V_DD Monitor Supply 
Current
—
300
—
ns
—
7
—
µA
Rev. 1.3
59