C8051F93X Datasheet, PDF (128/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 10.1. AC Parameters for External Memory Interface
Parameter
T_ACS
T_ACW
T_ACH
T_ALEH
T_ALEL
T_WDS
T_WDH
T_RDS
T_RDH
Description
Address/Control Setup Time
Address/Control Pulse Width
Address/Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
Write Data Hold Time
Read Data Setup Time
Read Data Hold Time
Min
0
1 x T_SYSCLK
0
1 x T_SYSCLK
1 x T_SYSCLK
1 x T_SYSCLK
0
20
0
Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Max
3 x T_SYSCLK
16 x T_SYSCLK
3 x T_SYSCLK
4 x T_SYSCLK
4 x T_SYSCLK
19 x T_SYSCLK
3 x T_SYSCLK
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
128
Rev. 1.3