C8051F93X Datasheet, PDF (294/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
25.2.2. 8-bit Timers with Auto-Reload
When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-
ate in auto-reload mode as shown in Figure 25.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH
holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control for TMR2H. TMR2L is
always running when configured for 8-bit Mode.
Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, SmaRTClock divided by 8 or
Comparator 0 output. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or
the clock defined by the Timer 2 External Clock Select bits (T2XCLK[1:0] in TMR2CN), as follows:
T2MH
0
0
0
0
1
T2XCLK[1:0] TMR2H Clock
Source
00
SYSCLK / 12
01
SmaRTClock / 8
10
Reserved
11
Comparator 0
X
SYSCLK
T2ML
0
0
0
0
1
T2XCLK[1:0] TMR2L Clock
Source
00
SYSCLK / 12
01
SmaRTClock / 8
10
Reserved
11
Comparator 0
X
SYSCLK
The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows
from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time
TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is
generated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check
the TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt
flags are not cleared by hardware and must be manually cleared by software.
T2XCLK[1:0]
SYSCLK / 12
00
SmaRTClock / 8
01
Comparator 0
11
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL 10
0
TR2
1
SYSCLK
1
0
TMR2RLH ^Reload
TCLK _TMR2H
TMR2RLL ^Reload
TCLK _TMR2L
To SMBus
TF2H
TF2L
TF2LEN
TF2CEN
T2SPLIT
TR2
T2XCLK
To ADC,
SMBus
Figure 25.5. Timer 2 8-Bit Mode Block Diagram
Interrupt
294
Rev. 1.3