C8051F93X Datasheet, PDF (220/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
21.2.2. Assigning Port I/O Pins to Digital Functions
Any Port pins not assigned to analog functions may be assigned to digital functions or used as GPIO. Most
digital functions rely on the Crossbar for pin assignment; however, some digital functions bypass the
Crossbar in a manner similar to the analog functions listed above. Port pins used by these digital func-
tions and any Port pins selected for use as GPIO should have their corresponding bit in PnSKIP set
to 1. Table 21.2 shows all available digital functions and the potential mapping of Port I/O to each digital
function.
Table 21.2. Port I/O Assignment for Digital Functions
Digital Function
Potentially Assignable Port Pins
UART0, SPI1, SPI0, SMBus, Any Port pin available for assignment by the
CP0 and CP1 Outputs, Sys- Crossbar. This includes P0.0–P2.6 pins which
tem Clock Output, PCA0,
have their PnSKIP bit set to 0.
Timer0 and Timer1 External Note: The Crossbar will always assign UART0 and
Inputs.
SPI1 pins to fixed locations.
Any pin used for GPIO
P0.0–P2.6
External Memory Interface
P1.0–P2.6
SFR(s) used for
Assignment
XBR0, XBR1, XBR2
P0SKIP, P1SKIP,
P2SKIP
P1SKIP, P2SKIP
EMI0CF
21.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions
External digital event capture functions can be used to trigger an interrupt or wake the device from a low
power mode when a transition occurs on a digital I/O pin. The digital event capture functions do not require
dedicated pins and will function on both GPIO pins (PnSKIP = 1) and pins in use by the Crossbar (PnSKIP
= 0). External digital even capture functions cannot be used on pins configured for analog I/O. Table 21.3
shows all available external digital event capture functions.
Table 21.3. Port I/O Assignment for External Digital Event Capture Functions
Digital Function
External Interrupt 0
External Interrupt 1
Port Match
Potentially Assignable Port Pins
P0.0–P0.7
P0.0–P0.7
P0.0–P1.7
Note: On C8051F931/21 devices Port Match is not
available on P1.6 or P1.7.
SFR(s) used for
Assignment
IT01CF
IT01CF
P0MASK, P0MAT
P1MASK, P1MAT
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Rev. 1.3