HD6413008VF25 Datasheet, PDF (99/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

φ
Address bus
Read
access
Internal read signal
Internal data bus
Write
access
Internal write signal
Internal data bus
T₁ state
Bus cycle
T₂ state
2. CPU
T₃ state
Address
Read data
Write data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
T₁
T₂
T₃
φ
Address bus
Address
AS, RD, HWR, LWR
D₁₅ to D₀
High
High impedance
Figure 2.18 Pin States during Access to On-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area is accessed via an 8-bit or 16-bit data bus, and whether it is accessed
in two or three states. For details see section 6, Bus Controller.
Rev.4.00 Aug. 20, 2007 Page 53 of 638
REJ09B0395-0400