HD6413008VF25 Datasheet, PDF (619/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TCNT—Timer Counter
H'FFF8D (read), H'FFF8C (write)
WDT
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
RSTCSR—Reset Control/Status Register
Bit
7
6
5
WRST RSTOE
⎯
Initial value
0
0
1
Read/Write R/(W)*
R/W
⎯
H'FFF8F (read), H'FFF8E (write)
WDT
4
3
⎯
⎯
1
1
⎯
⎯
2
1
0
⎯
⎯
⎯
1
1
1
⎯
⎯
⎯
Reset output enable
0 External output of reset signal is disabled
1 External output of reset signal is enabled
Watchdog timer reset
0 ^{[Clearing conditions]}
• Reset signal at RES pin
• Read WRST when WRST = 1, then write 0 in WRST
[Setting condition]
1 _{TCNT overflow generates a reset signal during watchdog timer}
operation
Note: * Only 0 can be written in bit 7 to clear the flag.
Rev.4.00 Aug. 20, 2007 Page 573 of 638
REJ09B0395-0400