HD6413008VF25 Datasheet, PDF (265/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Value of 16TCNT0
to 16TCNT2
GRB0
GRB1
GRA0
GRB2
GRA1
GRA2
H'0000
TIOCA₀
8. 16-Bit Timer
Cleared by compare match with GRB0
TIOCA₁
TIOCA₂
Figure 8.25 Synchronization (Example)
8.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB compare match is selected as the counter
clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin.
PWM mode can be selected in all channels (0 to 2).
Table 8.4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
Rev.4.00 Aug. 20, 2007 Page 219 of 638
REJ09B0395-0400