HD6413008VF25 Datasheet, PDF (166/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
Output
of
CS
4
to
CS₇:
Output
of
CS
4
to
CS
7
is
enabled
or
disabled
in
the
chip
select
control
register (CSCR). A reset leaves pins CS₄ to CS₇ in the input state. To output chip select signals CS₄
to CS₇, the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports.
φ
Address bus
External address in area n
CSn
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
When
the
on-chip
ROM,
on-chip
RAM,
and
internal
I/O
registers
are
accessed,
CS
0
to
CS
7
remain
high. The CS_n signals are decoded from the address signals. They can be used as chip select
signals for SRAM and other devices.
6.3.5 Address Output Method
The H8/3008 provides a choice of two address update methods: either the same method as in the
previous H8/300H Series (address update mode 1), or a method in which address updating is
restricted to external space accesses (address update mode 2).
Figure 6.5 shows examples of address output in these two update modes.
On-chip
memory cycle
External
read cycle
On-chip
memory cycle
External
read cycle
On-chip
memory cycle
Address bus
(Address update
mode 1)
Address bus
(Address update
mode 2)
RD
Figure 6.5 Sample Address Output in Each Address Update Mode
(Basic Bus Interface, 3-State Space)
Rev.4.00 Aug. 20, 2007 Page 120 of 638
REJ09B0395-0400