HD6413008VF25 Datasheet, PDF (322/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. 8-Bit Timers
9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, counter clearing by
the input capture signal takes priority and the counter is not incremented. The value before the
counter is cleared is transferred to TCORB. Figure 9.22 shows the timing in this case.
φ
Input capture signal
Counter clear signal
8TCNT internal clock
8TCNT
N
H'00
TCORB
X
N
Figure 9.22 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev.4.00 Aug. 20, 2007 Page 276 of 638
REJ09B0395-0400