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HD6413008VF25 Datasheet, PDF (502/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
17. Clock Pulse Generator
17.5.3 Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock
cycle
time
tcyc
in
the
AC
electrical
characteristics.
Note
that
φ
min
=
lower
limit
of
the
operating frequency range. Ensure that φ is not below this lower limit.
• All on-chip module operations are based on φ. Note that the timing of timer operations, serial
communication, and other time-dependent processing differs before and after any change in
the division ratio. The waiting time for exit from software standby mode also changes when
the division ratio is changed. For details, see section 18.4.3, Selection of Waiting Time for Exit
from Software Standby Mode.
Rev.4.00 Aug. 20, 2007 Page 456 of 638
REJ09B0395-0400