HD6413008VF25 Datasheet, PDF (263/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 8.23 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Input capture signal
16TCNT
N
GRA, GRB
N
Figure 8.23 Input Capture Signal Timing
8.4.3 Synchronization
The synchronization function enables two or more timer counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate 16TCR settings, two
or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 2).
Sample Setup Procedure for Synchronization: Figure 8.24 shows a sample procedure for
setting up synchronization.
Rev.4.00 Aug. 20, 2007 Page 217 of 638
REJ09B0395-0400