HD6413008VF25 Datasheet, PDF (55/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

1. Overview
Type
System
control
Symbol
RES
RESO
STBY
BREQ
BACK
Interrupts
Address
bus
NMI
IRQ
5
to
IRQ
0
A to A
23
0
Data bus
D₁₅ to D₀
Bus control
CS
7
to
CS
0
AS
RD
HWR
LWR
WAIT
Pin No.
FP-100B
TFP-100B
63
10
62
59
60
64
17, 16,
90 to 87
97 to 100,
56 to 45,
43 to 36
34 to 23,
21 to 18
2 to 5,
88 to 91
69
70
71
72
58
I/O
Input
Output
Input
Input
Output
Input
Input
Output
Input/
output
Output
Output
Output
Output
Output
Input
Name and Function
Reset input: When driven low, this pin resets the
chip. This pin must be driven low at power-up.
Reset output: Outputs the reset signal generated
by the watchdog timer to external devices
Standby: When driven low, this pin forces
a transition to hardware standby mode
Bus request: Used by an external bus master to
request the bus right
Bus request acknowledge: Indicates that the
bus has been granted to an external bus master
Nonmaskable interrupt: Requests a
nonmaskable interrupt
Interrupt request 5 to 0: Maskable interrupt
request pins
Address bus: Outputs address signals
Data bus: Bidirectional data bus
Chip select: Select signals for areas 7 to 0
Address strobe: Goes low to indicate valid
address output on the address bus
Read: Goes low to indicate reading from the
external address space
High write: Goes low to indicate writing to the
external address space; indicates valid data on
the upper data bus (D₁₅ to D₈).
Low write: Goes low to indicate writing to the
external address space; indicates valid data on
the lower data bus (D to D ).
7
0
Wait: Requests insertion of wait states in bus
cycles during access to the external address
space
Rev.4.00 Aug. 20, 2007 Page 9 of 638
REJ09B0395-0400