HD6413008VF25 Datasheet, PDF (243/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Bit 0—Overflow Flag 0 (OVF0): This status flag indicates 16TCNT0 overflow.
Bit 0
OVF0
0
1
Description
[Clearing condition]
Read OVF0 flag when OVF0 = 1, then write 0 in OVF0 flag
[Setting condition]
16TCNT0 overflowed from H'FFFF to H'0000
(Initial value)
8.2.7 Timer Counters (16TCNT)
16TCNT is a 16-bit counter. The 16-bit timer has three 16TCNTs, one for each channel.
Channel
0
1
2
Abbreviation
16TCNT0
16TCNT1
16TCNT2
Function
Up-counter
Phase counting mode: up/down-counter
Other modes: up-counter
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Each 16TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source.
The clock source is selected by bits TPSC2 to TPSC0 in 16TCR.
16TCNT0 and 16TCNT1 are up-counters. 16TCNT2 is an up/down-counter in phase counting
mode and an up-counter in other modes.
16TCNT can be cleared to H'0000 by compare match with GRA or GRB or by input capture to
GRA or GRB (counter clearing function).
When 16TCNT overflows (changes from H'FFFF to H'0000), the OVF flag is set to 1 in TISRC of
the corresponding channel.
When 16TCNT underflows (changes from H'0000 to H'FFFF), the OVF flag is set to 1 in TISRC
of the corresponding channel.
Rev.4.00 Aug. 20, 2007 Page 197 of 638
REJ09B0395-0400