HD6413008VF25 Datasheet, PDF (607/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
TISRC—Timer Interrupt Status Register C
H'FFF66 16-bit timer (all channels)
Bit:
Initial value:
Read/Write:
7
6
5
4
3
2
1
0
⎯ OVIE2 OVIE1 OVIE0 ⎯ OVF2 OVF1 OVF0
1
0
0
0
1
0
0
0
⎯ R/W R/W R/W ⎯ R/(W)* R/(W)* R/(W)*
Overflow flag 0
0 ^{[Clearing condition]}
Read OVF0 when OVF0 = 1, then write 0 in OVF0.
[Setting condition]
1
16TCNT0 overflowed from H'FFFF to H'0000.
(Initial value)
Overflow flag 1
0 ^{[Clearing condition]}
Read OVF1 when OVF1 = 1, then write 0 in OVF1.
[Setting condition]
1
16TCNT1 overflowed from H'FFFF to H'0000.
(Initial value)
Overflow flag 2
0 ^{[Clearing condition]}
Read OVF2 when OVF2 = 1, then write 0 in OVF2.
(Initial value)
[Setting condition]
1 16TCNT2 overflowed from H'FFFF to H'0000, or underflowed from H'0000
to H'FFFF.
Overflow interrupt enable 0
0 OVI0 interrupt requested by OVF0 flag is disabled
1 OVI0 interrupt requested by OVF0 flag is enabled
(Initial value)
Overflow interrupt enable 1
0 OVI1 interrupt requested by OVF1 flag is disabled
1 OVI1 interrupt requested by OVF1 flag is enabled
(Initial value)
Overflow interrupt enable 2
0 OVI2 interrupt requested by OVF2 flag is disabled
1 OVI2 interrupt requested by OVF2 flag is enabled
Note: * Only 0 can be written to clear the flag.
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 561 of 638
REJ09B0395-0400