HD6413008VF25 Datasheet, PDF (319/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. 8-Bit Timers
9.7.2 Contention between 8TCNT Write and Increment
If an increment pulse occurs in the T₃ state of a 8TCNT write cycle, writing takes priority and
8TCNT is not incremented. Figure 9.19 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
Address bus
8 TCNT address
Internal write signal
8TCNT input clock
8TCNT
N
M
8TCNT write data
Figure 9.19 Contention between 8TCNT Write and Increment
Rev.4.00 Aug. 20, 2007 Page 273 of 638
REJ09B0395-0400