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| HD6413008VF25 Datasheet, PDF (51/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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1.2 Block Diagram
Figure 1.1 shows an internal block diagram.
1. Overview
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
RESO
NMI
Ï/P67
LWR
HWR
RD
AS
BACK/P62
BREQ/P61
WAIT/P60
CS0/P84
ADTRG/CS1/IRQ3/P83
CS2/IRQ2/P82
CS3/IRQ1/P81
IRQ0/P80
Port 3
Address bus
Data bus (upper)
Data bus (lower)
Port 4
H8/300H CPU
Interrupt controller
RAM
16-bit timer unit
8-bit timer unit
Programmable
timing pattern
controller (TPC)
Watchdog timer
(WDT)
Serial communication
interface
(SCI) Ã 2 channels
A/D converter
D/A converter
Port B
Port A
Port 7
A 19
A 18
A 17
A 16
A 15
A 14
A 13
A 12
A 11
A 10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD 1
P90/TxD 0
Note: * The 5 V operation models have a VCL pin, and require the connection of an external capacitor.
Figure 1.1 Block Diagram
Rev.4.00 Aug. 20, 2007 Page 5 of 638
REJ09B0395-0400
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