HD6413008VF25 Datasheet, PDF (117/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Exception Handling
4.3 Interrupts
Interrupt exception handling can be requested by seven external sources (NMI, IRQ₀ to IRQ₅), and
27 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources
and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
timer, 8-bit timer, serial communication interface (SCI), and A/D converter. Each interrupt source
has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts ^{NMI (1)}
IRQ₀ to IRQ₅ (6)
Internal interrupts
WDT^* (1)
16-bit timer (9)
8-bit timer (8)
SCI (8)
A/D converter (1)
Notes: Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt
request at every counter overflow.
Figure 4.4 Interrupt Sources and Number of Interrupts
4.4 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1
in CCR. If the UE bit is 0, the I and UI bits are both set to 1 in CCR. The TRAPA instruction
fetches a start address from a vector table entry corresponding to a vector number from 0 to 3,
which is specified in the instruction code.
Rev.4.00 Aug. 20, 2007 Page 71 of 638
REJ09B0395-0400