HD6413008VF25 Datasheet, PDF (498/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

17. Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 17.3 shows the clock timing, figure 17.6
shows the external clock input timing, and figure 17.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t_DEXT) has passed after the clock input. The system
must remain reset with the reset signal low during t_DEXT, while the clock output is unstable.
Table 17.3 Clock Timing (Preliminary)
V_CC = 3.0 V
to 3.6 V
V_CC = 5.0 V
±10 %
Item
Symbol Min Max Min Max
External clock input low t_EXL
pulse width
15 ⎯
15 ⎯
External clock input high t_EXH
pulse width
15 ⎯
15 ⎯
External clock rise time t_EXr
External clock fall time t_EXf
Clock low pulse width
t
CL
⎯5
⎯5
0.4 0.6
80 ⎯
⎯5
⎯5
0.4 0.6
80 ⎯
Clock high pulse width t
CH
0.4 0.6
80 ⎯
0.4 0.6
80 ⎯
External clock output
settling delay time
t_DEXT*
500 ⎯
500 ⎯
Note: * t_DEXT includes a RES pulse width (t_RESW). t_RESW = 20 t_cyc
Unit
ns
ns
ns
ns
t
cyc
ns
t
cyc
ns
μs
Test Conditions
Figure 17.6
φ ≥ 5 MHz Figure
φ < 5 MHz ^19.7
φ ≥ 5 MHz
φ < 5 MHz
Figure 17.7
Rev.4.00 Aug. 20, 2007 Page 452 of 638
REJ09B0395-0400