HD6413008VF25 Datasheet, PDF (274/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.35 shows the timing.
φ
16TCNT
Overflow
signal
OVF
OVI
Figure 8.35 Timing of Setting of OVF
8.5.2 Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8.36 shows the timing.
TISR write cycle
T₁
T₂
T₃
φ
Address
TISR address
IMF, OVF
Figure 8.36 Timing of Clearing of Status Flags
Rev.4.00 Aug. 20, 2007 Page 228 of 638
REJ09B0395-0400