HD6413008VF25 Datasheet, PDF (320/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. 8-Bit Timers
9.7.3 Contention between TCOR Write and Compare Match
If a compare match occurs in the T₃ state of a TCOR write cycle, writing takes priority and the
compare match signal is inhibited. Figure 9.20 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
8TCNT
N
N+1
TCOR
Compare match signal
N
M
TCOR write data
Inhibited
Figure 9.20 Contention between TCOR Write and Compare Match
Rev.4.00 Aug. 20, 2007 Page 274 of 638
REJ09B0395-0400