HD6413008VF25 Datasheet, PDF (131/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit
7
⎯
Initial value
0
Read/Write
⎯
5. Interrupt Controller
6
5
4
3
2
1
0
⎯ IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
0
0
0
0
0
0
0
⎯ R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Reserved bits
Note: * Only 0 can be written, to clear flags.
IRQ ₅ to IRQ₀ flags
These bits indicate IRQ ₅ to IRQ₀ flag
interrupt request status
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can not be modified and are always read as 0.
Bits 5 to 0—IRQ₅ to IRQ₀ Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ₅ to
IRQ₀ interrupt requests.
Bits 5 to 0
IRQ5F to IRQ0F Description
0
[Clearing conditions]
(Initial value)
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5 to 0
5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ₅ to IRQ₀ interrupt requests.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯ IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved bits
IRQ ₅ to IRQ₀ enable
These bits enable or disable IRQ ₅ to IRQ ₀ interrupts
IER is initialized to H'00 by a reset and in hardware standby mode.
Rev.4.00 Aug. 20, 2007 Page 85 of 638
REJ09B0395-0400