HD6413008VF25 Datasheet, PDF (168/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
6.4 Basic Bus Interface
6.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL
(see table 6.3).
6.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D₁₅ to D₈) or lower data bus (D₇ to D₀) is used according to the bus specifications
for the area being accessed (8-bit access area or 16-bit access area) and the data size.
8-Bit Access Areas: Figure 6.7 illustrates data alignment control for 8-bit access space. With 8-bit
access space, the upper data bus (D₁₅ to D₈) is always used for accesses. The amount of data that
can be accessed at one time is one byte: a word access is performed as two byte accesses, and a
longword access, as four byte accesses.
Byte size
Upper data bus
Lower data bus
D₁₅
D₈ D₇
D₀
Word size
1st bus cycle
2nd bus cycle
Longword size
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area)
16-Bit Access Areas: Figure 6.8 illustrates data alignment control for 16-bit access areas. With
16-bit access areas, the upper data bus (D₁₅ to D₈) and lower data bus (D₇ to D₀) are used for
accesses. The amount of data that can be accessed at one time is one byte or one word, and a
longword access is executed as two word accesses.
Rev.4.00 Aug. 20, 2007 Page 122 of 638
REJ09B0395-0400