HD6413008VF25 Datasheet, PDF (353/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Programmable Timing Pattern Controller (TPC)
10.4 Usage Notes
10.4.1 Operation of TPC Output Pins
TP₀ to TP₁₅ are multiplexed with 16-bit timer, address bus, and other pin functions. When 16-bit
timer, or address bus output is enabled, the corresponding pins cannot be used for TPC output. The
data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
10.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 10.9 illustrates the non-overlapping TPC output operation.
DDR
Q
NDER
Q
Compare match A
Compare match B
TPC output pin
C
Q DR D
Q NDR D
Figure 10.9 Non-Overlapping TPC Output
Rev.4.00 Aug. 20, 2007 Page 307 of 638
REJ09B0395-0400