HD6413008VF25 Datasheet, PDF (318/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. 8-Bit Timers
9.7 Usage Notes
Note that the following kinds of contention can occur in 8-bit timer operation.
9.7.1 Contention between 8TCNT Write and Clear
If a timer counter clear signal occurs in the T₃ state of a 8TCNT write cycle, clearing of the
counter takes priority and the write is not performed. Figure 9.18 shows the timing in this case.
8TCNT write cycle
T1
T2
T3
φ
Address bus
8TCNT address
Internal write signal
Counter clear signal
8TCNT
N
H'00
Figure 9.18 Contention between 8TCNT Write and Clear
Rev.4.00 Aug. 20, 2007 Page 272 of 638
REJ09B0395-0400