HD6413008VF25 Datasheet, PDF (323/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. 8-Bit Timers
9.7.6 Contention between TCOR Write and Input Capture
If an input capture signal occurs in the T₃ state of a TCOR write cycle, input capture takes priority
and the write to TCOR is not performed. Figure 9.23 shows the timing in this case.
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
Internal write signal
Input capture signal
8TCNT
M
TCOR
X
M
Figure 9.23 Contention between TCOR Write and Input Capture
Rev.4.00 Aug. 20, 2007 Page 277 of 638
REJ09B0395-0400