HD6413008VF25 Datasheet, PDF (283/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Contention between General Register Write and Input Capture: If an input capture signal
occurs in the T₃ state of a general register write cycle, input capture takes priority and the write to
the general register is not performed. See figure 8.44.
General register write cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal write signal
Input capture signal
16TCNT
M
GR
M
Figure 8.44 Contention between General Register Write and Input Capture
Rev.4.00 Aug. 20, 2007 Page 237 of 638
REJ09B0395-0400