HD6413008VF25 Datasheet, PDF (616/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
8TCSR1—Timer Control/Status Register 1
H'FFF83
8-bit timer channel 1
Bit
7
6
5
4
CMFB CMFA OVF ICE
Initial value
0
0
0
0
Read/Write R/(W)* R/(W)* R/(W)* R/W
3
OIS3
0
R/W
2
OIS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Output select A1 and A0
Bit 1 Bit 0
OS1 OS0
Description
0 No change at compare match A
0
1 0 output at compare match A
0 1 output at compare match A
1 _{1 Output toggles at compare}
match A
Output/input capture edge select B3 and B2
ICE in Bit 3 Bit 2
8TCSR1 _{OIS3 OIS2}
Description
0 No change at compare match B
0
1 0 output at compare match B
0
0 1 output at compare match B
1
Output toggles at compare match
1B
0 ^{TCORB input capture on rising}
0
edge
1
1 ^{TCORB input capture on falling}
edge
0 TCORB input capture on both
1
1 ^{rising and falling edges}
Input capture enable
0 TCORB is a compare match register
1 TCORB is an input capture register
Timer overflow flag
[Clearing condition]
0 _{Read OVF when OVF = 1, then write 0 in OVF.}
1
[Setting condition]
8TCNT overflows from H'FF to H'00.
Compare match flag A
[Clearing condition]
0 _{Read CMFA when CMFA = 1, then write 0 in CMFA.}
1
[Setting condition]
8TCNT = TCORA
Compare match/input capture flag B
0 ^{[Clearing condition]}
Read CMFB when CMFB = 1, then write 0 in CMFB.
[Setting conditions]
1 ^{• 8TCNT = TCORB}
• The 8TCNT value is transferred to TCORB by an input capture signal when
TCORB functions as an input capture register.
Note: * Only 0 can be written to bits 7 to 5 to clear these flags.
Rev.4.00 Aug. 20, 2007 Page 570 of 638
REJ09B0395-0400