HD6413008VF25 Datasheet, PDF (16/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
12.3.2 Operation in
Asynchronous Mode
Figure 12.4 Sample
Flowchart for SCI
Initialization
Page
356
13.3.5 Clock
396
Table 13.5 Bit Rates
(bits/s) for Various BRR
Settings (When n = 0)
Table 13.6 BRR
397
Settings for Typical Bit
Rates (bits/s) (When n =
0)
18.4.3 Selection of 466
Waiting Time for Exit
from Software Standby
Mode
Table 18.3 Clock
Frequency and Waiting
Time for Clock to Settle
19.2 DC
476
Characteristics
Table 19.2 DC
Characteristics (2)
Revision (See Manual for Details)
Figure amended and note added
(4) Wait for at least the interval required to transmit or receive
one bit, then set the TE or RE bit to 1 in SCR*. Set the RIE,
TIE, TEIE, and MPIE bits as necessary. Setting the TE or
RE bit enables the SCI to use the TxD or RxD pin.
Note: * In simultaneous transmitting and receiving, the TE and
RE bits should be cleared to 0 or set to 1
simultaneously.
Table amended
φ (MHz)
N
18.00 20.00 25.00
0
24193.5 26881.7 33602.2
1
12096.8 13440.9 16801.1
2
8064.5 8960.6 11200.7
Table amended
bit/s
9600
φ (MHz)
18.00
20.00
25.00
N Error N Error N Error
2 15.99 2 6.66 3 12.49
Table amended
DIV1 DIV0 STS2 STS1 STS0 Waiting Time 6 MHz
01 0
0 0 8192 states 2.7
0
0 1 16384 states 5.5
0
1 0 32768 states 10.9*
0
1 1 65536 states 21.8
1
0 0 131072 states 43.7
1
0 1 262144 states 87.4
1
1 0 1024 states 0.34
1
11
4 MHz 2 MHz 1MHz Unit
4.1 8.2* 16.4* ms
8.2* 16.4 32.8
16.4 32.8 65.5
32.8 65.5 131.1
65.5 131.1 262.1
131.1 262.1 524.3
0.51 1.0 2.0
Illegal setting
Table amended
Item
Symbol Min
Current
Standby mode I_CC*³
⎯
dissipation*²
⎯
Analog power During A/D
AI_CC
⎯
supply current conversion
During A/D
⎯
and D/A
conversion
Idle
⎯
Typ
Max
1.0
10
⎯
80
0.6
1.5
0.6
1.5
0.01
5.0
Rev.4.00 Aug. 20, 2007 page xiv of xliv
REJ09B0395-0400