HD6413008VF25 Datasheet, PDF (27/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13.3.5 Clock.................................................................................................................... 396
13.3.6 Transmitting and Receiving Data......................................................................... 398
13.4 Usage Notes ...................................................................................................................... 406
Section 14 A/D Converter ................................................................................................. 411
14.1 Overview........................................................................................................................... 411
14.1.1 Features................................................................................................................ 411
14.1.2 Block Diagram ..................................................................................................... 412
14.1.3 Pin Configuration................................................................................................. 413
14.1.4 Register Configuration......................................................................................... 414
14.2 Register Descriptions ........................................................................................................ 415
14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 415
14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 416
14.2.3 A/D Control Register (ADCR) ............................................................................ 418
14.3 CPU Interface.................................................................................................................... 419
14.4 Operation........................................................................................................................... 421
14.4.1 Single Mode (SCAN = 0)..................................................................................... 421
14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 423
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 425
14.4.4 External Trigger Input Timing ............................................................................. 427
14.5 Interrupts ........................................................................................................................... 427
14.6 Usage Notes ...................................................................................................................... 428
Section 15 D/A Converter ................................................................................................. 435
15.1 Overview........................................................................................................................... 435
15.1.1 Features................................................................................................................ 435
15.1.2 Block Diagram ..................................................................................................... 436
15.1.3 Pin Configuration................................................................................................. 437
15.1.4 Register Configuration......................................................................................... 437
15.2 Register Descriptions ........................................................................................................ 438
15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 438
15.2.2 D/A Control Register (DACR) ............................................................................ 438
15.2.3 D/A Standby Control Register (DASTCR) .......................................................... 440
15.3 Operation........................................................................................................................... 440
15.4 D/A Output Control .......................................................................................................... 442
Section 16 RAM .................................................................................................................. 443
16.1 Overview........................................................................................................................... 443
16.1.1 Block Diagram ..................................................................................................... 444
16.1.2 Register Configuration......................................................................................... 444
Rev.4.00 Aug. 20, 2007, Page xxv of xliv
REJ09B0395-0400