HD6413008VF25 Datasheet, PDF (340/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Programmable Timing Pattern Controller (TPC)
10.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP₁₅ to TP₈) on a bit-by-bit basis.
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W R/W
R/W
R/W R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the 16-bit timer compare match event
selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically
transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled,
the bit value is not transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP₁₅ to TP₈) on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8
0
1
Description
TPC outputs TP to TP are disabled
15
8
(NDR15 to NDR8 are not transferred to PB₇ to PB₀)
TPC outputs TP₁₅ to TP₈ are enabled
(NDR15 to NDR8 are transferred to PB to PB )
7
0
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 294 of 638
REJ09B0395-0400