HD6413008VF25 Datasheet, PDF (233/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 2. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
7
6
5
4
⎯
MDF FDIR
⎯
1
0
0
1
⎯
R/W R/W
⎯
3
2
1
0
⎯ PWM2 PWM1 PWM0
1
0
0
0
⎯
R/W
R/W
R/W
Reserved bit
PWM mode 2 to 0
These bits select PWM
mode for channels 2 to 0
Flag direction
Selects the setting condition for the overflow
flag (OVF) in TISRC
Phase counting mode flag
Selects phase counting mode for channel 2
Reserved bit
TMDR is initialized to H'98 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF
0
1
Description
Channel 2 operates normally
Channel 2 operates in phase counting mode
(Initial value)
When MDF is set to 1 to select phase counting mode, 16TCNT2 operates as an up/down-counter
and pins TCLKA and TCLKB become counter clock input pins. 16TCNT2 counts both rising and
falling edges of TCLKA and TCLKB, and counts up or down as follows.
Rev.4.00 Aug. 20, 2007 Page 187 of 638
REJ09B0395-0400