HD6413008VF25 Datasheet, PDF (15/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
Page
9.7.6 Contention
277
between TCOR Write
and Input Capture
Figure 9.23 Contention
between TCOR Write
and Input Capture
Revision (See Manual for Details)
Figure amended
TCOR write cycle
T1
T2
T3
φ
Address bus
TCOR address
9.7.7 Contention
278
between 8TCNT Byte
Write and Increment in
16-Bit Count Mode
(Cascaded Connection)
Figure 9.24 Contention
between 8TCNT Byte
Write and Increment in
16-Bit Count Mode
Internal write signal
Input capture signal
8TCNT
M
TCOR
X
M
Description amended
If an increment pulse occurs in the T₂ or T₃ state of an 8TCNT
byte write cycle in 16-bit count mode, the counter write takes
priority and the byte data for which the write was performed is
not incremented. The byte data for which a write was not
performed is incremented. Figure 9.24 shows the timing when
an increment pulse occurs in the T₂ state of a byte write to
8TCNT (upper byte). If an increment pulse occurs in the T₂
state, on the other hand, the increment takes priority.
Figure amended
8TCNT (upper byte) byte write cycle
T1
T2
T3
φ
Address bus
8TCNTH address
Internal write signal
8TCNT input clock
8TCNT (upper byte)
8TCNT (lower byte)
N
N+1
8TCNT write data
X
X+1
Rev.4.00 Aug. 20, 2007, Page xiii of xliv
REJ09B0395-0400