HD6413008VF25 Datasheet, PDF (381/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Serial Communication Interface
Bit 2—Transmit-End interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2
TEIE
Description
0
Transmit-end interrupt requests (TEI) are disabled*
(Initial value)
1
Transmit-end interrupt requests (TEI) are enabled*
Note: * TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in
SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by
clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): The function of these bits differs for the
normal serial communication interface and for the smart card interface. Their function is switched
with the SMIF bit in SCMR.
For serial communication interface (SMIF bit in SCMR cleared to 0): These bits select the
SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings
of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or
serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). Select the SCI operating mode in SMR before setting the
CKE1 and CKE0 bits . For further details on selection of the SCI clock source, see table 12.9 in
section 12.3, Operation.
Bit 1 Bit 0
CKE1 CKE0 Description
0
0
Asynchronous mode Internal clock, SCK pin available for generic input/output*¹
Synchronous mode Internal clock, SCK pin used for serial clock output*¹
0
1
Asynchronous mode Internal clock, SCK pin used for clock output*²
Synchronous mode Internal clock, SCK pin used for serial clock output
1
0
Asynchronous mode External clock, SCK pin used for clock input*³
Synchronous mode External clock, SCK pin used for serial clock input
1
1
Asynchronous mode External clock, SCK pin used for clock input*³
Synchronous mode External clock, SCK pin used for serial clock input
Notes: 1. Initial value
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 times the bit rate.
Rev.4.00 Aug. 20, 2007 Page 335 of 638
REJ09B0395-0400