HD6413008VF25 Datasheet, PDF (158/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
BCR is an 8-bit readable/writable register that enables or disables idle cycle insertion, selects the
area division unit, selects the extended memory map, and enables or disables WAIT pin input.
BCR is initialized to H'C6 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read cycles for different areas.
Bit 7
ICIS1
0
1
Description
No idle cycle inserted in case of consecutive external read cycles for different
areas
Idle cycle inserted in case of consecutive external read cycles for different
areas
(Initial value)
Bit 6—Idle Cycle Insertion 0 (ICIS0): Selects whether one idle cycle state is to be inserted
between bus cycles in case of consecutive external read and write cycles.
Bit 6
ICIS0
0
1
Description
No idle cycle inserted in case of consecutive external read and write cycles
Idle cycle inserted in case of consecutive external read and write cycles
(Initial value)
Bits 5 to 3—Reserved (must not be set to 1): These bits can be read and written, but must not be
set to 1. Normal operation cannot be guaranteed if 1 is written in these bits.
Bit 2— Reserved (must not be set to 0): This bit can be read and written, but must not be set to
0. Normal operation cannot be guaranteed if 0 is written in this bit.
Rev.4.00 Aug. 20, 2007 Page 112 of 638
REJ09B0395-0400