HD6413008VF25 Datasheet, PDF (557/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. Block transfer instructions
Addressing Mode and
Instruction Length (bytes)
Appendix A Instruction Set
No. of
States*¹
Mnemonic
EEPMOV. B
⎯
EEPMOV. W
⎯
Condition Code
Operation
I HNZVC
4 if R4L ≠ 0
⎯⎯⎯⎯⎯⎯
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L−1 → R4L
until R4L=0
else next;
8+4n*²
4 if R4 ≠ 0
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4−1 → R4
until R4L=0
else next;
⎯⎯⎯⎯⎯⎯
8+4n*²
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory. For other cases see section
A.3, Number of States Required for Execution.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Rev.4.00 Aug. 20, 2007 Page 511 of 638
REJ09B0395-0400