HD6413008VF25 Datasheet, PDF (118/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Exception Handling
4.5 Stack Status after Exception Handling
Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP−4
SP−3
SP−2
SP−1
SP (ER7) ^→
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
CCR
CCR *
PC _H
PC _L
Even address
Before exception handling
After exception handling
Pushed on stack
a. Normal mode
SP−4
SP−3
SP−2
SP−1
SP (ER7) ^→
Stack area
SP (ER7) →
SP+1
SP+2
SP+3
SP+4
CCR
PC _E
PC _H
PC _L
Even address
Before exception handling
After exception handling
Pushed on stack
b. Advanced mode
Legend:
PC_E: Bits 23 to 16 of program counter (PC)
PC_H: Bits 15 to 8 of program counter (PC)
PC_L: Bits 7 to 0 of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: PC indicates the address of the first instruction that will be executed after return.
Registers must be saved in word or longword size at even addresses.
* Ignored at return.
Figure 4.5 Stack after Completion of Exception Handling
Rev.4.00 Aug. 20, 2007 Page 72 of 638
REJ09B0395-0400