HD6413008VF25 Datasheet, PDF (181/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
In (a), an idle cycle is not inserted, and a collision occurs in bus cycle B between the read data
from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is
prevented.
φ
Address bus
Bus cycle A Bus cycle B
T1 T2 T3 T1 T2
φ
Address bus
Bus cycle A Bus cycle B
T1 T2 T3 Ti T1 T2
RD
HWR
Data bus
RD
HWR
Data bus
Data collision
Long buffer-off time
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1)
Usage Note: When non-insertion of an idle cycle is specified, the rise (negation) of RD and fall
(assertion)
of
CS
n
may
occur
simultaneously.
Figure
6.20
shows
an
example
of
the
operation
in
this case.
If consecutive reads to a different external area occur while the ICIS1 bit in BCR is cleared to 0, or
if an external read is followed by a write cycle for a different external area while the ICIS0 bit is
cleared
to
0,
negation
of
RD
in
the
first
read
cycle
and
assertion
of
CS
n
in
the
following
bus
cycle
will occur simultaneously. Depending on the output delay time of each signal, therefore, it is
possible that the RD low output in the previous read cycle and the CS_n low output in the following
bus cycle will overlap.
As
long
as
RD
and
CS
n
do
not
change
simultaneously,
or
if
there
is
no
problem
even
if
they
do,
non-insertion of an idle cycle can be specified.
Rev.4.00 Aug. 20, 2007 Page 135 of 638
REJ09B0395-0400