HD6413008VF25 Datasheet, PDF (537/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

19. Electrical Characteristics
19.6.3 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 19.7 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 19.8 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 19.9 shows the timing of the external three-state access cycle with one wait state
inserted.
• Bus-release mode timing
Figure 19.10 shows the bus-release mode timing.
Rev.4.00 Aug. 20, 2007 Page 491 of 638
REJ09B0395-0400