HD6413008VF25 Datasheet, PDF (165/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)
ABWCR ASTCR WCRH/WCRL
ABWn ASTn Wn1 Wn0
0
0
⎯
⎯
1
0
0
1
1
0
1
1
0
⎯
⎯
1
0
0
1
1
0
1
Note: n = 0 to 7
Bus Specifications (Basic Bus Interface)
Bus Width Access States
Program Wait States
16
2
0
3
0
1
2
3
8
2
0
3
0
1
2
3
6.3.3 Memory Interfaces
As its memory interface, the H8/3008 has only a basic bus interface that allows direct connection
of ROM, SRAM, and so on. It is not possible to select a DRAM interface that allows direct
connection of DRAM, or a burst ROM interface that allows direct connection of burst ROM.
6.3.4 Chip Select Signals
For each of areas 0 to 7, the H8/3008 can output a chip select signal (CS₀ to CS₇) that goes low
when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of
a CSn signal.
Output
of
CS
0
to
CS₃:
Output
of
CS
0
to
CS
3
is
enabled
or
disabled
in
the
data
direction
register
(DDR) of the corresponding port.
In
the
expanded
modes
with
on-chip
ROM
disabled,
a
reset
leaves
pin
CS
0
in
the
output
state
and
pins CS₁ to CS₃ in the input state. To output chip select signals CS₁ to CS₃, the corresponding DDR
bits
must
be
set
to
1.
In
the
expanded
modes
with
on-chip
ROM
enabled,
a
reset
leaves
pins
CS
0
to
CS₃ in the input state. To output chip select signals CS₀ to CS₃, the corresponding DDR bits must
be set to 1. For details, see section 7, I/O Ports.
Rev.4.00 Aug. 20, 2007 Page 119 of 638
REJ09B0395-0400