HD6413008VF25 Datasheet, PDF (281/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T₃ state of a general register read cycle, the value before input capture is read.
See figure 8.42.
General register read cycle
T₁
T₂
T₃
φ
Address bus
GR address
Internal read signal
Input capture signal
GR
X
M
Internal data bus
X
Figure 8.42 Contention between General Register Read and Input Capture
Rev.4.00 Aug. 20, 2007 Page 235 of 638
REJ09B0395-0400