HD6413008VF25 Datasheet, PDF (148/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
CS0 to CS7
Internal address bus
Area
decoder
Chip select
control signals
ABWCR
ASTCR
BCR
CSCR
ADRCR
Bus control
circuit
Internal signals
Bus mode control signal
Bus size control signal
Access state control signal
Wait request signal
WAIT
Internal signals
CPU bus request signal
CPU bus acknowledge signal
Wait state
controller
WCRH
WCRL
BRCR
Bus arbiter
Legend:
ABWCR: Bus width control register
ASTCR: Access state control register
WCRH: Wait control register H
WCRL: Wait control register L
BRCR: Bus release control register
CSCR: Chip select control register
ADRCR: Address control register
BCR: Bus control register
BACK
BREQ
Figure 6.1 Block Diagram of Bus Controller
Rev.4.00 Aug. 20, 2007 Page 102 of 638
REJ09B0395-0400