HD6413008VF25 Datasheet, PDF (378/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12. Serial Communication Interface
12.2.6 Serial Control Register (SCR)
SCR register enables or disables the SCI transmitter and receiver, enables or disables serial clock
output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock
source.
Bit
7
6
5
TIE
RIE
TE
Initial value
0
0
0
Read/Write
R/W
R/W
R/W
4
3
2
1
0
RE
MPIE
TEIE
CKE1 CKE0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Clock enable 1/0
These bits select the
SCI clock source
Transmit-end interrupt enable
Enables or disables transmit-end
interrupts (TEI)
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Receive enable
Enables or disables the receiver
Transmit enable
Enables or disables the transmitter
Receive interrupt enable
Enables or disables receive-data-full interrupts (RxI) and
receive-error interrupts (ERI)
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TxI)
The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby
mode.
Rev.4.00 Aug. 20, 2007 Page 332 of 638
REJ09B0395-0400