HD6413008VF25 Datasheet, PDF (238/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8. 16-Bit Timer
8.2.5 Timer Interrupt Status Register B (TISRB)
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables GRB compare match and input capture interrupt requests.
Bit
Initial value
Read/Write
7
6
5
4
3
⎯ IMIEB2 IMIEB1 IMIEB0 ⎯
1
0
0
0
1
⎯
R/W R/W R/W
⎯
2
1
0
IMFB2 IMFB1 IMFB0
0
0
0
R/(W)* R/(W)* R/(W)*
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
Reserved bit
Reserved bit
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
Note: * Only 0 can be written, to clear the flag.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 when IMFB2 flag is set to 1.
Bit 6
IMIEB2
0
1
Description
IMIB2 interrupt requested by IMFB2 flag is disabled
IMIB2 interrupt requested by IMFB2 flag is enabled
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 192 of 638
REJ09B0395-0400