HD6413008VF25 Datasheet, PDF (614/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Appendix B Internal I/O Registers
8TCR0—Timer Control Register 0
8TCR1—Timer Control Register 1
H'FFF80
H'FFF81
8-bit timer channel 0
8-bit timer channel 1
Bit
7
6
CMIEB CMIEA
Initial value
0
0
Read/Write R/W
R/W
5
4
3
2
OVIE CCLR1 CCLR0 CKS2
0
0
0
0
R/W
R/W
R/W
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Clock select 2 to 0
0 Clock input is disabled
0
1
Internal clock: counted on rising
edge of φ/8
0
0 Internal clock: counted on rising
1
edge of φ/64
1 ^{Internal clock: counted on rising}
edge of φ/8192
Channel 0:
Count on 8TCNT1 overflow signal*
0 ^{Channel 1:}
0
Count on 8TCNT0 compare match
A*
1
1 External clock: counted on falling edge
0 External clock: counted on rising edge
1
External clock: counted on both
1 _{rising and falling edges}
Note: * If the clock input of channel 0 is the 8TCNT1
overflow signal and that of channel 1 is the
8TCNT0 compare match signal, no
incrementing clock is generated. Do not use
this setting.
Counter clear 1 and 0
0
0
1
Clearing is disabled
Cleared by compare match A
0
1
1
Cleared by compare match B/input capture B
Cleared by input capture B
Timer overflow interrupt enable
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
Compare match interrupt enable A
0 CMIA interrupt requested by CMFA is disabled
1 CMIA interrupt requested by CMFA is enabled
Compare match interrupt enable B
0 CMIB interrupt requested by CMFB is disabled
1 CMIB interrupt requested by CMFB is enabled
Rev.4.00 Aug. 20, 2007 Page 568 of 638
REJ09B0395-0400