HD6413008VF25 Datasheet, PDF (209/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7. I/O Ports
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
Bit
7
6
5
4
3
2
1
0
PA₇DDR PA₆DDR PA₅DDR PA₄DDR PA₃DDR PA₂DDR PA₁DDR PA₀DDR
Modes ^{Initial value 1}
0
0
0
0
0
0
0
3 and 4 _{Read/Write ⎯}
W
W
W
W
W
W
W
Modes
1 and 2
Initial value
0
0
0
0
0
0
0
0
Read/Write W
W
W
W
W
W
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
The pin functions that can be selected for pins PA₇ to PA₄ differ between modes 1 and 2, and
modes 3 and 4. For the method of selecting the pin functions, see tables 7.12 and 7.13.
The pin functions that can be selected for pins PA₃ to PA₀ are the same in modes 1 to 4. For the
method of selecting the pin functions, see table 7.14.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA₇DDR is fixed at 1 and PA₇ functions as the A₂₀ address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1 and 2. It is
initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby
mode it retains its previous setting. Therefore, if a transition is made to software standby mode
while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding
pin maintains its output state.
Rev.4.00 Aug. 20, 2007 Page 163 of 638
REJ09B0395-0400