HD6413008VF25 Datasheet, PDF (105/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

3. MCU Operating Modes
Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an interrupt mask bit.
Bit 3
UE
0
1
Description
UI bit in CCR is used as an interrupt mask bit
UI bit in CCR is used as a user bit
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the valid edge of the NMI input.
Bit 2
NMIEG
0
1
Description
An interrupt is requested at the falling edge of NMI
An interrupt is requested at the rising edge of NMI
(Initial value)
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS₀ to CS₇, AS, RD, HWR, LWR) are kept as outputs or fixed high, or placed
in the high-impedance state in software standby mode.
Bit 1
SSOE
0
1
Description
In software standby mode, the address bus and bus control signals are all high-
impedance
(Initial value)
In software standby mode, the address bus retains its output state and bus control
signals are fixed high
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by the rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
Rev.4.00 Aug. 20, 2007 Page 59 of 638
REJ09B0395-0400