HD6413008VF25 Datasheet, PDF (182/688 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Bus Controller
φ
Address bus
RD
CSn
Bus cycle A Bus cycle B
T1 T2 T3 T1 T2
φ
Address bus
RD
CSn
Bus cycle A Bus cycle B
T1 T2 T3 Ti T1 T2
Simultaneous change of RD and
CSn: possibility of mutual overlap
(a) Idle cycle not inserted
(b) Idle cycle inserted
Figure 6.20 Example of Idle Cycle Operation
6.5.2 Pin States in Idle Cycle
Table 6.5 shows the pin states in an idle cycle.
Table 6.5 Pin States in Idle Cycle
Pins
A₂₃ to A₀
D₁₅ to D₀
CSn
AS
RD
HWR
LWR
Pin State
Next cycle address value
High impedance
High
High
High
High
High
Rev.4.00 Aug. 20, 2007 Page 136 of 638
REJ09B0395-0400